FPGA Logic Design – Adders, Multiplexers, and Gate Assembly

Executive Summary

The lecture explains how basic logic gates (AND, OR, XOR, NOT) are combined to build half‑ and full‑adders, and how these adders are chained on an FPGA to perform binary addition. It also outlines the plan to cover multiplexers and demultiplexers in the next session and emphasizes using the FPGA’s programmable logic for both simple gates and advanced applications such as neuromorphic computing.

Key Takeaways

• Gate Assembly: Build complex circuits by wiring IC gates on a schematic screen; the FPGA executes the resulting logic.
• Half‑Adder: Uses an XOR for the sum and an AND for the carry‑out.
• Full‑Adder: Extends the half‑adder with an additional carry‑in input; sum = XOR of all three inputs, carry‑out = majority logic.
• Adder Chains: Connect multiple full‑adders to handle multi‑bit addition; carry‑in from one feeds carry‑out of the previous.
• FPGA Flexibility: A clean‑slate board can implement simple logic, neural‑network interfaces, and higher‑level AI functions.
• Upcoming Topics: Multiplexers, demultiplexers, and parity checkers will be covered in the next lecture.

Detailed Summary

1. FPGA Logic Implementation

• Place logic gates on the FPGA schematic screen.
• The board interprets the schematic as hardware, allowing dynamic reprogramming.
• Enables integration with external devices (cameras, neural nets, etc.).

2. Basic Logic Gates

• AND: Generates carry‑out when both inputs are 1.
• XOR (Exclusive OR): Produces the sum bit; outputs 1 only when inputs differ.
• NOT / Inverter: Used to create XOR from AND, OR, and NOT combinations.

3. Half‑Adder

• Inputs: A, B.
• Outputs: Sum (XOR of A and B), Carry‑Out (AND of A and B).
• Truth table:

  A	B	Sum	Carry
  0	0	0	0
  0	1	1	0
  1	0	1	0
  1	1	0	1

4. Full‑Adder

• Inputs: A, B, Carry‑In (CI).
• Outputs: Sum (XOR of A, B, CI), Carry‑Out (majority of A, B, CI).
• Implemented by connecting two half‑adders:
  1. First half‑adder sums A and B.
  2. Second half‑adder adds the first sum to CI.
  3. Carry‑Out = OR of the two half‑adder carry outputs.
• Truth table:

  A	B	CI	Sum	CO
  0	0	0	0	0
  0	0	1	1	0
  0	1	0	1	0
  0	1	1	0	1
  1	0	0	1	0
  1	0	1	0	1
  1	1	0	0	1
  1	1	1	1	1

5. Adder Chains for Multi‑Bit Addition

• Least significant bit uses a half‑adder (no carry‑in).
• Subsequent bits use full‑adders; carry‑out of one feeds carry‑in of the next.
• The chain propagates carries leftward across bit positions.

6. FPGA Programming Flow

1. Design: Create logic gate network on schematic.
2. Simulate: Verify truth tables and timing.
3. Compile: Generate bitstream for the FPGA.
4. Deploy: Load onto hardware; observe real‑time operation.

7. Future Modules

• Multiplexers / Demultiplexers: Channel multiple data sources through a single line.
• Parity Checkers: Detect errors in binary data.
• These will be constructed using the same gate‑assembly methodology.

Takeaway: Complex arithmetic and data routing functions can be built from a handful of basic gates, and the FPGA’s reconfigurable architecture turns these designs into live hardware with minimal effort.